The present invention relates to a method for transferring DMA data. More particularly to a method for transferring DMA data between the video port and the host interface in a multimedia processor.
In a modem personal computer (PC), most PC buses make provisions for giving expansion boards control over the Direct Memory Access (DMA) controllers in the computer host. This way, the microprocessor itself need not be burdened with controlling the expansion bus. Instead, the microprocessor delegates the control of the bus to special circuitry dedicated to the task, i.e., a DMA controller. In addition, DMA operations can also be used to move data between I/O devices and memory. Modem PCs that use a DMA controller typically integrate this circuitry with the rest of the system support inside the chipset. For operation, the DMA controller inside this specialized chip must know the base location of where bytes are to be moved from, the address to where the bytes should go, and the number of bytes to move. The specific DMA controller used in all IBM.RTM. computers is completely programmable and after it has received the necessary information from the host microprocessor, is operated through a series of I/O registers.
Recently, highly-integrated multimedia integrated circuits (ICs) have been developed that individually replace close to half a dozen expansion boards. These chips are designed to eliminate payment for duplicated logic and memories, and complicated set-up configurations in high-end multimedia subsystems. One example of such a multimedia IC is the Mpact media processor developed by Chromatic Research Inc. The Mpact media processor is described in "Reprogrammable IC Takes On Graphics, Video, and Audio," by Dave Bursky, in Electronic Design/Oct. 13, 1995, pp.133-137, and the related description is incorporated herein by reference.
This particular multimedia IC is based on a programmable very-long-instruction-word (VLIW) engine that performs single-instruction/multiple-data (SIMD) operations and vector processing. The VLIW approach and the multiple on-chip processing blocks combine to give the chip elements of both supercomputers and digital signal processors. This also allows the chip to achieve the high throughput needed to simultaneously handle a wide assortment of multimedia tasks, replacing a collection of dedicated boards.
The configuration of a conventional Mpact processor is schematically shown in FIG. 1. The Mpact processor comprises a PCI bus 10, a Mpact chip 20, an RDRAM frame buffer 50, a video system 60, and a RAMDAC 70. The Mpact multimedia chip 20 comprises a 32-bit PCI interface 22, dedicated DMA, Read, and Write FIFO buffers 25, 26, and 28, a VLIW processor block 30, a video interface 40, a video FIFO buffer 42, a display interface 45, a frame buffer controller 46, and a display FIFO buffer 47.
As shown in FIG. 2, the VLIW processor block 30 comprises four arithmetic and logic units (ALUs) 38, an instruction decoder 36, an instruction fetch 34, and an SRAM 32 that serves as a DMA register file as shown in FIG. 2. The long instruction word can be used to program each computational block simultaneously so that many parallel operations can be performed during each clock cycle.
The frame buffer controller 46, which may be a high-bandwidth Rambus DRAM interface, is connected to the RDRAM frame buffer 50 and has sufficient bandwidth for video data streams. The 32-bit PCI interface 22 is provided to allow data transfers between the chip and the host system or from PCI to PCI device. The PCI interface 22 is connected to the dedicated DMA, Read, and Write FIFO buffers 25, 26, and 28 for DMA, Read, and Write operations, respectively. Data moves between the on-chip SRAM 32 and the external RDRAM frame buffer 50 at a high data transfer rate, for example up to 500 Mbytes/sec through the frame buffer controller 46. This high data rate ensures that the various computational blocks on the chip are never waiting to send or receive data between the host bus and the off-chip DRAM 50 used to hold image data.
The display bus port or display interface 45 and the a display FIFO buffer 47 tie into the off-chip RAMDAC 70, which in turn can drive an RGB monitor. The video bus port or video interface 40 and the video FIFO buffer 42 can either handle direct digital video data, or tie into the off-chip video system 60 that includes video ADCs and DACs for capturing or delivering analog NTSC/PAL video signals. The frame buffer controller 46 uses the DMA controller to move data in and out of the RDRAM buffer 50 without host intervention. Also, the DMA controller manages data transfers between the host interface 22 and the video interface 40. The DMA register 32 of the VLIW processor block 30 stores a data transfer count required for DMA operation, a frame buffer read/write address, a host bus read/write address, and a status information informing start/end of the DMA operation.
The DMA operation in the video port 40 is performed normally at under 4-kbyte wide data per instruction. This is because the largest bandwidth of the digital video format receivable in the video port 40 is 22.1 Mbyte/sec, in case of PAL video signals. This digital image data is transferred to the host interface 22 in 4-kbyte units by a DMA instruction. Also, the digital image data is transferred to the host memory in 4-kbyte units. Thus, the host microprocessor should load the DMA instruction onto the DMA controller as many as one frame image data is transferred to the host interface. Consequently, the host microprocessor exhausts almost all of its processing ability in programming the DMA controller. This will deteriorate system performance as well as system speed.
Thus, when DMA operations are performed in the multimedia IC to move data between a video port and a host interface, and when large amounts of data must be transferred, the microprocessor will have to frequently load the DMA instructions into the DMA controller. This can severely reduce CPU performance in programming the DMA controller and can deteriorate the video data transfer rate.